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  • John Barney

John Barney

Graduate Student | PhD

Email:
barneyjo@iu.edu
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Bio

John Barney is a Ph.D. candidate in Intelligent Systems Engineering at Indiana University Bloomington and a research assistant under the advisement of Dr. Daniel Loveless. He earned his B.S. in Electrical Engineering from the University of Tennessee at Chattanooga, where he also conducted research as an undergraduate assistant. John’s research focuses on understanding how radiation-induced charge from energetic ions is collected in semiconductor devices, how this charge forms single-event transients (SETs), and how those transients propagate through circuits to produce system-level effects. He is particularly interested in charge sharing between multiple sensitive volumes and its impact on single-event effects (SEEs), a critical challenge for highly scaled CMOS technologies operating in radiation-prone environments.

Research

Single-Event Effects Modeling

These figures illustrate the device-level TCAD modeling approach used to study radiation-induced charge collection in CMOS technologies. A two-dimensional Synopsys Sentaurus TCAD model representative of a bulk 90 nm n-type MOSFET is shown near X=0, Y=0 under nominal operating conditions (left) and an energetic ion strike (right). The resulting current density distributions capture the charge collection mechanisms responsible for single-event transients (SETs) measurements. These simulations were used to evaluate the impact of substrate tap spacing and guard ring implementation on the measured SET waveform shape. 

These figures illustrate the abstraction of physics-based TCAD results into ideal electrical components for circuit-level analysis. This compact modeling approach enables efficient evaluation of single-event upset (SEU) response without reliance on computationally intensive physics-based solvers. A conventional n-type MOSFET (NFET) is shown on the left, while the right depicts a current-source implementation used to emulate a single-event transient (SET). The current source is placed between the drain and body of the NFET to represent charge collection in the p–n junction, with the pulse shape reflecting the underlying charge collection behavior. Ongoing work focuses on implementing current sources across multiple transistors to represent charge sharing effects.

To enable large-scale circuit-level single-event upset (SEU) analysis, a custom software package, RadSim, was developed to automatically inject current-source compact models at every net of a circuit.

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