Adam Hubbard

Bio

I study the reliability of commercial off-the-shelf (COTS) NOR flash memory used to store boot code and mission-critical firmware in radiation environments. My work takes a lifecycle view of devices, examining how radiation-induced memory errors may change as devices move from "fresh" lab parts to field-challenged parts with a real operational history. Space and defense programs test and approve parts early in a project, but these devices may see manufacturing variability, updates, and field-tested issues that can shift the mission risk in ways that a one-time qualification test may not reveal. 

Rad-hard components are the ideal solution to this problem, especially for mission-critical functions. Technologies like SONOS (silicon-oxide-nitride-oxide-silicon) charge trap flash (CTF) are already marketed for their improved radiation tolerance over floating-gate flash memory, but even in rad-tolerant technologies, these errors could be reduced further with additional tuning knobs. My work aims to expose those tuning options to enable design engineers to act on cost-effective pathways to higher resilience when using COTS parts without needing to strive specifically for rad-hard parts.

Research

Electrical Stress vs. Single-Event Sensitivity in Charge-Trapping NOR Flash

This research project focuses on SONOS-based memories, a charge-trapping class of flash that stores information using traps in a nitride layer called the charge-trapping layer (CTL). While radiation effects in 3D NAND charge-trap memories have been studied extensively as of late, MirrorBit™ and NROM-style charge-trapping NOR devices have received less attention, comparatively. It is worth emphasizing this gap in research because these architectures can store two bits per cell by doping the nitride layer to be capable of storing two bits per cell with localized charge storage regions in the nitride. This offers higher densities compared to floating-gate-based NOR flash and the increased radiation tolerance benefits of SONOS-based memories.

Many NOR flash devices, including the Infineon S29GL064S line of chips used in this project, incorporate embedded error detection/correction (ECC) features. These tools can make radiation effects appear invisible to the user, at least until the device crosses a margin where ECC can no longer keep up with accumulating bit upsets, like in the case of two upset bits within the same 32-byte page region. In this study, the S29GL064S was evaluated using both fresh memory sectors and regions that had undergone advanced program/erase cycling, enabling a direct comparison of upset behavior under controlled irradiation at Lawrence Berkeley National Laboratory (LBNL).