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  • Lucas Nichols

Lucas Nichols

Graduate Student | PhD

Email:
nicholuc@iu.edu

Bio

As a PhD student in CREATE at Indiana University, my research focuses on the design and implementation of radiation-hardened-by-design integrated circuits, specifically targeting phase-locked loops within advanced technology nodes.

With semiconductor scaling following the trajectory of Moore's law, conventional radiation hardening techniques become increasingly challenged by the complexities of modern transistor architectures. By building upon foundational research in generalized single-event effect models, my research expands upon the predictive, model-based framework to characterize radiation-induced output phase displacements and to mitigate worst-case circuit response.

Research

Single-Event Upset Modeling In Phase Lock Loops

In the analysis of radiation effects on Phase-Locked Loops (PLLs), the failure mechanism is modeled by linking the metric of error (output phase displacement) with the stability threshold (critical time constant).

Output phase displacement: time integral of the instantaneous frequency deviation caused by single-event transients.

Critical time constant: temporal threshold that determines whether a single-event transient will be suppressed by the PLL or cause a Single Event Upset.

Mathematically, this behavior follows a kinematic hierarchy:

  • Phase jitter ↔ position

  • Period jitter ↔ velocity

  • Cycle-to-cycle jitter ↔ acceleration

Visual distinctions between Phase Jitter, Period Jitter, and Cycle-to-Cycle Jitter

Ku-Band LC-Tank Digitally Controlled Oscillator in Bulk FinFET

Designed and fabricated a LC-tank Digitally Controlled Oscillator (DCO) operating in the Ku-band (12-18 GHz) utilizing an advanced Bulk FinFET process. The design incorporates a current mode logic output buffer to maintain signal integrity while driving the off-chip interface via wire-bond packaging.

The project overcomes the following challenges of implementing analog RF circuits within a FinFET technology:

  • Fin width quantization

  • Layout design rule management

  • High-frequency layout dependent effects

  • Parasitic minimization, extraction and back-annotation

Leveraged RadSim (see below) to perform radiation sensitivity analysis on the DCO to characterize its radiation response.

3D Layout Visualization of the Fabricated Circuit

RadSim - Radiation Simulation

RadSim is an automation framework designed to streamline the simulation of radiation effects within Cadence Virtuoso Layout Suite.

RadSim is a result of the collaborative development between:

  • Lucas Nichols (SKILL): Responsible for the direct interactions with the Cadence Virtuoso cell views, database and simulation kernel

  • John Barney(Python): Responsible for the simulation configuration, automation control, and data analysis

Regarding the technical implementation of the SKILL code, it uses the primary modules:

  • Get Nets: extracts netlists, device parameters, and connectivity information from schematic cell views, exporting results in a structured XML format

Run Sim: automates simulation setup, execution, and results collection in ADE Assembler, supporting configurable test types and exporting waveform data for further analysis

D Flip-Flop Single Event Upset Simulation Profile. The plot illustrates two radiation test cases "Hold 1" and "Hold 0" with features: Ion Strike: red vertical lines (marked with lightning bolts) indicate the injection time of the simulated particle strike Trigger Window: blue hatched regions represent the failure detection windows for the desired signal
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