- Email:
- trpeyton@iu.edu
Bio
Trevor is a PhD student studying how radiation affects artificial intelligence systems, coming from a computer science and AI background. His research focuses on understanding what happens to machine learning models when radiation hits the hardware they run on, specifically systolic arrays, which are the core computing structure in modern AI chips. To study this properly, he's designed and built custom AI accelerators that let him measure and understand exactly how radiation causes faults in these systems.
Trevor also started his own company where he's fabricated an AI accelerator and a RISC-V CPU with a built-in AI accelerator. This matters because AI is now being used everywhere, in satellites, spacecraft, aircraft. Right now, we don't fully understand how these AI chips break down when hit by radiation. His work aims to provide a deep, practical understanding of what happens to systolic array accelerators under radiation so we can build AI systems that are more reliable in harsh environments and mission-critical applications.
Research
Fault Injection In Deep Neural Networks
Brute force fault injection study
Over 50 models were studied
100 billion test samples
Took over 1000 GPU hours
What the study looks for is simple but important. When does a single bit flip cause the AI model to give a completely wrong answer? These are called critical silent data corruptions, and they're dangerous because the system doesn't crash or give an error, it just confidently gives the wrong thing. The results show that yes, a single bit can cause a total misprediction. This data helps understand which parts of neural networks are most vulnerable to radiation so researchers know where to focus protection efforts.
Three AI Accelerator Chip Designs
Trevor has designed three AI accelerators
One with the University, two with his own company ArrayFold
Systolic Array Test chip - MIT90 - IU
Study the effects of radiation effects on systolic array architectures
16x16 Reconfigurable (8-bit, 4-bit, 2-bit, 1-bit) weight and activations
Reconfigurable Output, Input, or weight stationary data flow
Accelerator - GF180 - ArrayFold
Radiation Tollerant design
4KB SRAM
32x32 Output Stataionary fixed dataflow
RISC-V accelerator - GF180 - ArrayFold
Radiation Tollerant design
Contains an 8x8 embedded output stationary systolic array
16KB SRAM, QSPI, SPI, I2C, UART, PWM, watchdog, timers, instruction cache, PLIC
Systolic Array Test Chip
A custom chip has been designed and built through the university specifically for studying radiation effects on AI hardware. Fabricated in a 90nm process, this chip is instrumented for research. It has special circuitry that allows viewing the complete internal state after radiation hits it, with protected control systems so it keeps running during tests. The chip can be reconfigured to test different computing modes and data types, which allows understanding how different design choices affect radiation sensitivity.
The chip features different quantized modes:
8-bit, 4-bit, 2-bit, 1-bit, and ternary weights
8-bit, 4-bit, 2-bit, 1-bit activations
It also supports reconfigurable data patterns:
Output Statationary
Weight Stationary
Input Stationary
Two Commercial Accelerators for Space Applications
Separately, Trevor founded a company, ArrayFold, and has fabricated two commercial chips in a 180nm process. The first (below) is a 32x32 AI accelerator that's fully radiation-hardened. Having an array this large at this process node is impressive.
The second chip is a complete system: a radiation-hardened RISC-V CPU with an embedded 8x8 AI accelerator. The CPU has configurable protection, built-in memory, and supports standard communication protocols for real applications. These chips demonstrate commercially viable products. The goal is to show the market opportunity and use this as a foundation to move to smaller, faster chips that can run larger AI models in space and other harsh environments.
